Telink Second Generation Testbench

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Overview

The Telink second generation testbench uses the TLSR8266 chip and is used for testing various PCB boards based on Telink chips, including power consumption in different modes, read and write of Flash/SRAM, Deep sleep/Suspend function, frequency bias calibration, RF transmit and receive, and burning function. The second generation testbench supports simultaneous testing of up to 8 devices and each device can be tested individually.

This document mainly introduces the hardware used for the testbench, the test connection method and script configuration, and uses the TLSR951X Demo Fixture as an example to help users quickly familiarise and use this testbench.

Hardware Introduction

Hardware of the Testbench

The hardware included in the Telink second generation testbench is listed below:

No.	Category	Name	Quantity	Description
1	Main board	Second generation testbench base board	1	Testbench base board
2	JIG EVK	Second generation testbench sub-board	8	Testbench sub-board, which is inserted into the base board for use.
3	Display board	Button/LEDs external board	1	The LED/Button external board used for convenient fixture testing.
4	General accessories	Whip antenna	8	Used in conjunction with JIG EVK
5	General accessories	DC 9V/2A power adapter	1	Supply power to the base board
6	General accessories	USB Cable	1	Type-A to Type-C USB Cable, connect the base board and the PC, and connect it to the "HUB" port on the base board.
7	General accessories	RF Cable	8	JIG EVK sub-board RF external extension cable
8	Custom accessories	Type-C to Type-C cable	2	Custom Type-C to Type-C cable for connecting the base board and the Button/LEDs external board

Main Hardware Introduction

Testbench Base Board

The base board mainly performs the following functions:

(1) Connect the JIG EVK sub-board and support up to 8 sites [The interface is shown at position 3 of the red box in the following figure].

(2) Connect the Button/LEDs external board via a custom Type-C cable [The interface is shown at position 5 of the red box in the following figure].

(3) Supply power to the test system:

a. Power supply to the base board and JIG EVK sub-board circuit [The interface is shown at position 1 of the red box in the following figure];

b. Reserve long output 3.3V & 5V [The interface is shown at position 4 of the red box in the following figure].

(4) Support the HUB function to achieve communication between the sub-board and the host computer of the end PC. Currently, it supports up to 8 sites [The interface is shown in the red box at position 2 in the following figure].

(5) It provides two methods for the DUT (Device Under Test) test interface [The interface is shown at position 6 of the red box in the following figure] :

a. Method 1: 2 x 2.54mm pitch header, the customer can short to the DUT with 2.54mm pitch cable;

b. Method 2: Provides three groups of Type-C interfaces, which can be connected to the DUT with customised Type-C cables; in this case, the same Type-C interface board needs to be made for the customer's DUT to connect with it.

Testbench JIG EVK Sub-board

The Sub-board is the core board used for testing. The JIG EVK is connected to the base board by headers, and each JIG EVK is connected to one DUT board.

Power supply: When used alone, it is powered by USB-5V; When used in conjunction with the base board, it is powered by 5V from the base board.

Main Functional Specifications:

(1) Supports TXCO, Tolerance: \pm 2.5ppm;

(2) Use SMA-FEMALE RF connector by default, connect antenna or RF cable externally;

(3) Different DUT power supply voltages can be provided:

a. ADJ-LDO supports output voltage: 3.3V/2.8V/2.5V/2.1V/1.8V;

b. Support controllable 5V power supply voltage, and can be used in 5V power supply applications such as Dongle.

(4) Supports high-precision current detection;

(5) Supports GPIO communication of different voltages;

(6) Supports OTP burning;

(7) Supports eFuse burning;

(8) Supports Type-C USB:

a. When the JIG EVK single board is in use, it is powered by Type-C USB and communicates with the PC host computer.

b. When JIG EVK is on the base board, it is powered by the boase board and communicates with the PC host computer through the base board HUB circuit.

Introduction to the Hardware Interface of JIG EVK Sub-board:

(1) JIG EVK sub-board burning interface:

• Burning via USB Type-C.

• Burning [PIN01: SWS] through SWS, as shown in the position of the red box in the following figure.

(2) Long output 5V and long output 3.3V interfaces, refer to the following figure.

(3) The DUT test interface, refer to the following figure.

(4) LED and function button: the four LEDs and two buttons correspond to the IO port allocation, refer to the following figure.

Button/LEDs External Board

(1) The Button/LEDs External Board is a sub-board for use with the customer's fixture. It can be used to control individual SITE tests or the whole test by pressing the buttons on the board.

• SITEX (X represents 1~8): corresponds to 8 SITEs tested individually;

• MAIN SW: All SITE tests.

(2) The board is connected to the base board through the Type-C USB interface at the right end and the custom Type-C to Type-C cable.

(3) It provides three LED color indication states: red, yellow and green.

(4) The left side of the board is reserved for the BUSY status pin interface.

General Accessories

A 2.4GHz whip antenna, USB Type-C cable, DC 9V/2A power adapter and RF Cable are provided in the hardware.

• 2.4GHz whip antenna: Used in projects such as DUT RF testing and frequency bias calibration;

• USB Type-C cable: The base board HUB circuit communicates with the host computer via the USB cable;

• DC 9V/2A power adapter: Supply power to the system;

• RF Cable: RF extension wiring, SMA-MALE to SMA-FEMALE.

Custom Accessories

Custom Type-C to Type-C cable is a connecting cable made with 24-pin USB Type-C male connector, the connectors on both ends correspond one to another, mainly used as a wire.

Custom cable purpose:

(1) Connect the base board and the Button/LEDs external board;

(2) Connect the base board and the DUT board.

Note:

Customers are required to reserve the corresponding Type-C interface when making DUT fixtures, and Telink provides the corresponding Type-C interface definition and packaging.

Currently, the base board supports two ways of connecting the DUT board, which the customer can choose according to their needs:

(1) Use the flexbile flat cables;

(2) Use the custom Type-C cable.

Hardware Connection of Testing

Hardware Connection Method

The hardware connection diagram is shown below:

Note:

(1) The JIG EVK sub-board RF socket faces upwards and connects with the base board, as shown in the yellow area in the figure above. (2) The Button/LEDs external board requires two custom cables. (3) For DUT, select custom cable or other applicable cable connection as required. (4) The antenna is fixed in position in coordination with the RF Cable according to the actual environment of the fixture.

DC-9V Power Connection for Base Board

Use the DC adapter in the kit to plug into a power socket to power the base board as shown below:

Base Board HUB Circuit Interface

The USB Type-C interface marked as 'HUB' on the base board is used to connect to the test computer and communicate with the host computer software, as shown in the figure below:

Connect JIG EVK Sub-board and Base Board

Plug the 8 JIG EVK sub-boards into the base board interface positions correspondingly (the sub-boards were inserted into the base board when the kit was shipped), as shown in the figure below:

Connect Base Board and DUT

The base board has two forms of DUT test interfaces:

(1) Site0 ~ Site7 8 groups of 2x10-2.54mm pitch pin header interfaces.

a. The red box position in the figure is the header interface net name definition, 8 groups of pins net name definition is the same;

b. The wiring between the base board and the DUT is as follows:

    - V-DUT: supply power to the DUT, connect to the VCC of the DUT, different voltages can be configured according to requirements;

    - V-REF: In order to match IO ports with different voltages, a level conversion circuit exists at the JIG EVK sub-board end, and the DUT end provides the IO port reference voltage to V-REF;

    - SWM: Communication pin, connected to SWS of DUT;

    - GND: Ground, connected to GND of DUT;

(2) 3 groups of USB Type-C interfaces:

There are 3 Type-C interfaces at the location marked by the yellow box in the picture:

• Site0 ~ Site2 are integrated in the Data-01 Type-C interface;

• Site3 ~ Site5 are integrated in the Data-02 Type-C interface;

• Site6 ~ Site7 are integrated in the Data-03 Type-C interface;

Note:

When using this port to connect to the DUT, it is necessary for the customer to make the corresponding Type-C interface for connection when making the fixture, Telink provides the network definition of the interface and the device package or device manual.

Supplement Description on V-REF:

The new fixture platform is compatible with other IOs of different voltages and has added the level shifting circuitry, so the interface with the DUT requires additional V-REF wiring, which is also a more obvious difference from the previous fixture wiring.

Therefore, during the subsequent application board design, it is recommended to increase the IO port reference voltage test points.

In order to be compatible with the customer's previous hardware design, an adjustable ADJ-LDO circuit has been added to the base board, which is used to simulate the IO port level of the DUT and serve as the DUT reference level of the level conversion circuit. Three adjustable voltage levels are provided: 1.8V, 2.5V, and 3.3V. The specific operations are as follows:

(1) Set the LDO output voltage V-OP (the configuration of the V-OP output voltage can refer to the silkscreen description next to the dipswitch) using dipswitch U119 on the base board (red box position in the figure below);

(2) Short-circuit V-REF and V-OP using the jumper (as shown in the white jumper in the following figure);

(3) Then connect the base board to the DUT with the three wires V-DUT, SWM and GND.

Connection of Single JIG EVK Sub-board and DUT

When testing with the JIG EVK sub-board and DUT 1V1, the wiring is as follows:

The JIG EVK sub-board can provide different voltages to the DUT, and the corresponding VCC-DUT or 5V-DUT can be selected according to the actual situation:

(1) VCC-DUT available voltage: 3.3V/2.8V/2.5V/2.1V/1.8V, different voltage output from LDO is controlled by software;

(2) 5V-DUT available voltage: 5V.

Wiring of the Base Board to the Button/LEDs External Board

The base board and the Button/LEDs external board is connected via a custom Type-C interface cable, note the orientation when connecting, using the white acetate cloth as a reference surface:

(1) Two wires need to be connected, the base board and the Button/LEDs external board is connected according to the silkscreen correspondence;

(2) When both the base board and the external board are facing up, the white acetate cloth side of the connected wires stays on the same side (both facing up or down), as shown in the figure below:

DUT Power Supply Selection and Dipswitch Setting

There are two power supply paths for the DUT:

(1) 5V voltage supply & ADJ LDO supply;

(2) Among them, ADJ LDO can be configured by software to output different voltages (currently supports five voltages: 3.3V/2.8V/2.5V/2.1V/1.8V).

Each Site has a dual-channel dipswitch and the two channels correspond to silkscreen as 5V, 3V3 (3V3 is the ADJ LDO supply path).

a. The default 3V3 path dipswitch is dialled to the ON side to turn on, and the 5V path is dialled to the OFF side;

b. If a 5V supply is required, dial the 5V path switch to the ON side and the 3V3 to the OFF side.

Note:

DO NOT dial both channels to the ON side at the same time!

Script Configuration

This document uses the TLSR951X EVB as an example of the DUT.

Considerations before Script Configuration

(1) JIG EVK hardware pre-preparation (completed during production phase).

a. Hardware functional circuit confirmation

b. Burning the testbench_evk.bin that matches the hardware

c. Burning TP Parameters

d. JIG EVK encryption

(2) testbench_evk.bin should be placed in the path of EVK Monitor software, the path is as follows: EvkMonitor\config\bin.

Note:

If it is not the testbench_evk.bin that matches the hardware but an old bin, in the subsequent steps of downloading the script, the old bin under this path will be downloaded into the JIG EVK, resulting in the failure of the normal use.

(3) Make sure that the function test bin under the corresponding chip is the latest bin (take B91 as an example) released to avoid inaccurate or impossible test results caused by not the latest bin.

(4) Configure the number of DUT test in the EVK Monitor software.

The software defaults to 6 Site test interface, while the testbench is 8 Site, so it needs to manually modify the configuration file to 12 Site test interface. The path and the location of the changes are shown in the figure below:

Script Configuration

Configure the script using the EVK Monitor software, using the TLSR951X EVB as an example.

Software Login

Double-click the software icon and enter the corresponding Password to log in the corresponding privilege interface:

Using Templates to Generate Original Scripts

Click EVK -> Configure -> Default Template, open the template configuration screen:

Type Select:

(1) Select the chip type;

(2) If you need to burn firmware, select boot1/boot2/boot3 as required to import the firmware path;

(3) Switch the before and after configuration interfaces through arrows.

Config1:

• Crystal: Configure the crystal specifications, B91 chip uses 24M;

• Debug_level: Configure the level of detail of the Log that assists in the analysis, 3 being the most detailed.

The other two are generally not needed.

Protect_2M_Flash_Calib_Value:

(1) Protect the calibration value of the chip pre-burned in the factory to avoid erasing by mistake;

(2) The calibration value position can refer to the planning in the document "Flash Mapping".

Erase:

Remove the chip Flash protection and define the size of the Flash to be erased.

Sram_Cache:

Test the chip Sram & Cache for write and read operation.

Deep_Timer_Wakeup:

It is the deep sleep state power consumption test, set the time to enter Deep state, Deep power consumption threshold and Deep wake-up.

Suspend_Timer_Wakeup:

It is the Suspend state power consumption test, set the time to enter Suspend state, Suspend power consumption threshold and Suspend wake-up.

RF:

It includes DUT RF Tx power test, Rx packet receiving test and frequency bias calibration.

Burning:

The DUT burning test, which consists of 3 main parts as follows:

(1) MAC burning (subject to configuration);

(2) Firmware burning;

(3) Frequency bias calibration value burning.

After configuration, click the red pen button, the corresponding script will be generated automatically and the burning interface dialogue box will be popped up at the same time.

B91 Script Changes

There are still a few things that need to be manually changed or noted in the automatically generated scripts based on the templates. The host computer software will be optimized afterwards.

The path to the automatically generated script test.tls is as follows:

Open the script file and note the following:

(1) Add DUT supply voltage configuration statement: config[62] = X

The two commonly used voltage configurations are as follows:

a. config[62] =6  #VCC_DUT3.3V

b. config[62] =7  #5V_DUT

(2) Deep power consumption & Suspend power consumption tests require changing the test bin to dut_b91_pm_v0003.bin.

The current automatically generated script is dut_b91_pm_v0002.bin, which does not need to be manually modified after subsequent software updates.

(3) LED Indicator Configuration

The LED behaviour can be controlled on demand by modifying the script led_state(0x00,0x01,0x02,0x04,0x08) statement.

Explanation of the statements:

led_state(start_s,run_s1,run_s2,ok_s,err_s)

• start_s: LED status after this script has finished running;

• run_s1: LED state 1 when the script is running;

• run_s2: LED state 2 when the script is running;

• ok_s: end of script, LED status when test result is correct;

• err_s: end of script, LED status when test result is error.

All the above 5 states are controlled by the byte low 4 bits to control the 4 LEDs, the mapping relationship is as follows:

For example: 0x01---->0000 0001---->LED3 LED2 LED1 LED0---->PIN36 PIN35 PIN32 PIN31 (chip control pins).

Burning the Updated Script

(1) In addition to the changes mentioned above, it is also possible to make specific changes to the scripts according to the requirements (usually the FAE makes the changes and outputs them to the customer);

(2) After the script change is completed, save the script file and switch back to the Download screen in the Burning chapter, or you can re-open the Download screen via the path shown below:

(3) Clicking the 'Download' button will download the programme for each JIG EVK in turn.

EVK Self-test

(1) After burning the script, close the Download interface and go back to the main interface of the software to see the created test sequence, see the position marked by the red box in the figure below;

(2) Click the 'Check' button on the main interface to bring up the check interface, click the 'Check' button to do EVK self-test;

(3) Confirm that the EVK burning programme is correct, and close the Check interface after all SITEs show OK.

Create the Test Database

(1) If you run it for the first time in a day, clicking the 'Start' button will automatically create a database file in the Database folder, as shown below:

(2) After creating the database, the test 'RUN' is enabled by grey scale, you can do the subsequent corresponding test.

(3) The run_times after the RUN button is a customised number of tests, such as 8 SITE currently, each run will increase 8 cumulatively.

Example of Demo Fixture Production

This chapter uses the actual TLSR951X Demo fixture as an example to show the actual wiring, which can be used as a reference.

(1) Fix the base board on the fixture.

(2) Connect the base board and DUT wiring (V-REF is supplied by the base board for reference voltage).

a. Each Site connects 3 data cables to the DUT (VCC-DUT/SWM/GND).

b. Each Site JIG EVK RF PORT is connected to the whip antenna via the RF Cable.

c. During the RF coupling test, the whip antenna is as close as possible to the DUT antenna.

(3) Connect the base board and the Button/LEDs external board.

Connect the base board and the Button/LEDs external board via custom Type-C cables.

(4) Connect the DC-POWER and HUB Type-C cable.